Field
Various features relate to a solenoid inductor in a substrate.
Background
Planar inductors are made with a spiral and an overpass. Multiple turns are necessary to achieve inductance. However, multiple turns increases the area that the planar inductor occupies. FIG. 1 illustrates an example of a planar inductor 100. A shown in FIG. 1, the planar inductor 100 includes a set of windings 102, a first port 104, a via 106, and a second port 108. The planar inductor 100 is a planar inductor in a substrate. The set of windings 102 is a set of spiral interconnects that form 3.5 turns. The set of spiral interconnects is a metal layer on a substrate. The first port 104 is coupled to a first end of the set of windings 102. The via 106 is coupled to a second end of the set of windings 102. The second port 108 is coupled to the via 106. In some implementations, the second port 108 is a second metal layer (e.g., overpass layer).
The set of windings 102 have inners turns (e.g., 3.5 turns) that can cause eddy current loss to the outer turns. Such eddy current loss can reduce the quality factor (Q) of the inductor. As shown in FIG. 1, the via 106 is a large via, which adds a big and thick metallization in the middle of the inductor 100. The via 106 also degrades the quality factor of the inductor 100.
Therefore, there is a need for an improved inductor design for semiconductor devices. Ideally, such an inductor will have better inductance performance, lower resistance and better quality factor value, of the semiconductor device.